1. Field of the Invention
This invention relates to a reticle mask and a method for exposing a pattern for integrated circuits using the same. More particularly, it relates to a reticle mask providing an exposure pattern for forming a plurality of integrated circuits and a window serving as a blank pattern, the latter of which can be used to remove an incomplete photoresist pattern which may exist at a periphery region of a semiconductor substrate, thereby improving the yield ratio in the photolithographic method in manufacturing semiconductor integrated circuits.
2. Related Art and Other Consideration
One example of the manufacturing method for semiconductor integrated circuits is illustrated below.
Referring to FIG. 8(a), a SiO.sub.2 film 10, a SiN film 11 and a SiO.sub.2 film 12 are sequentially stacked on a silicon substrate to form a substrate film 34. Then, the substrate film 34 is covered with a photoresist film, which is followed by exposing and developing a pattern for integrated circuits to form a photoresist pattern 33 (refer to FIG. 8(b)).
Subsequently, the substrate film 34 is patterned by using the photoresist pattern 33 and a dry etching method (refer to FIG. 8(c)).
In the next step, a thin SiN film 35 and a thick SiO.sub.2 film 36 are sequentially stacked all over the substrate film 34, followed by an etching-back method to form a side wall layer formed of the SiN film 35 and the SiO.sub.2 film 36 (refer to FIG. 8(d)).
Following that, the SiO.sub.2 films 12 and 36 are removed (refer to FIG. 8(e)), thereby forming a semiconductor integrated circuit.
After coating a photoresist L on a wafer, the photoresist retained in a region on the periphery of a wafer is removed with a thinner. This step is called "edge rinse" (refer to FIG. 14).
Referring to FIGS. 13 and 14, in the edge rinse step, a the photoresist tends to deform at its periphery region M. Because a solvent used in the edge rinse, (for example, a thinner) may remain in admixture with the photoresist at the periphery region M, thickness at the periphery region M may be thinner than that of the other region L. When a mask pattern is transcribed on the photoresist in this state, the resulting photoresist pattern is very likely to collapse at the periphery region M.
Further, when such a collapsed photoresist pattern is used to form the substrate film into a pattern, lift-off failures are very likely to be caused in the process, which produces dusts, resulting in a reduced yield ratio.
The mechanism of reduction in the yield ratio is further explained below.
For example, a SiO.sub.2 film 10, a SiN film 11, and a SiO.sub.2 film 12 are sequentially stacked on a Si substrate to form a substrate film (refer to FIG. 12(a)) in the same manner as shown in FIG. 8(a). This is followed by the formation of a photoresist pattern 13 on the SiO.sub.2 film 12 (refer to FIG. 12(b)).
Subsequently, the substrate film 14 is subjected to a patterning step by dry etching (refer to FIG. 12(c)). However, the collapse of the photoresist pattern inhibits the formation of a desired substrate film, which will exert an unfavorable influence upon the subsequent steps.
In the next step, a thin SiN film and a thick SiO.sub.2 film are sequentially stacked on the Si substrate, and then an etch back process is conducted for forming the side wall layer. However, the absence of a desired shape in the substrate film prevents the SiN film and the SiO.sub.2 film from forming a side wall layer all over the side surface of the substrate film 14 (refer to FIG. 12(d)).
Following the above step, when removing the side wall formed of SiO.sub.2, the absence of an offset SiN film 35 (refer to FIG. 8(d)) results in removing the SiO.sub.2 film 10, 12 to lift off the SiN film 11, thereby producing dusts (refer to FIG. 12(e)), which reduces the yield ratio of semiconductor integrated circuits.
As described above, in the photolithographic method involved in manufacturing semiconductor integrated circuits, the exposure and the development of circuit pattern will result in the formation of incomplete chips on the periphery of wafers, which induces the collapse and the separation of photoresist patterns to reduce the yield ratio. FIG. 15 shows an example of a wafer in which photoresist patterns are collapsed. Since incomplete integrated circuit chips are formed on the chip C 40 shown in FIG. 15, the collapsed portion K of a photoresist pattern shown in FIG. 12(b) is produced on a wafer edge portion where photoresists are removed with edge rinse. In FIG. 15, a chip A 41 and a chip B 42 are complete while a chip C 40 is incomplete.
FIG. 16 shows a mask 50 used in exposing a pattern for forming an integrated circuit shown in FIG. 15. In FIG. 16, reference numeral 51 designates a Cr film forming an exposure window 52 for mutually independent chips A, B and C of integrated circuits.
Removing the chip C 40 which causes the pattern collapse K from a mask on which a plurality of integrated circuit chips are formed requires removing complete chips such as chip A 41 and chip B 42 within the same shot (refer to FIG. 11). Inhibiting the formation of incomplete chips has resulted in the inability of exposing complete units within the same shot on the periphery of wafers, thereby reducing the yield ratio of LSI's.
Japanese Laid-Open Patent No. 226750/1986 and Japanese Laid-Open Patent No. 38747/1989 describe a conventional photomask and an exposure processes using the same.
Japanese Laid-Open Patent No. 226750/1986 discloses a process of reflective projection in the ratio of 1:1 wherein the configuration portion which transmits ultraviolet ray is fixed, which makes it impossible for us to voluntarily concern ourselves with a location where photoresists are removed.
On the other hand, Japanese Laid-Open Patent No. 38747/1989 has a drawback of an inability of removing incomplete chips without reducing the size of the block of unit patterns.